Instruction Set (quick finder)

Instruction	Meaning	Earliest CPU / Comments
ABS	Absolute Value	Floating Point
ACS	Arc Cosine	Floating Point
ADC	Add with Carry	-
ADD	Add	-
ADF	Add	Floating Point
ADR	Get address of object (within 4K)	This is an assembler pseudo-instruction
ADRL	Get address of object (beyond 4K)	This is an assembler pseudo-instruction
ALIGN	Set the program counter to the next word boundary	This is an assembler pseudo-instruction
AND	Logical AND	-
ASL	Arithmetic Shift Left	This is an option, not an instruction
ASN	Arc Sine	Floating Point
ASR	Arithmetic Shift Right	This is an option, not an instruction
ATN	Arc Tangent	Floating Point
B	Branch	-
BIC	Bit Clear	-
BL	Branch with Link	-
BX	Branch to Thumb code	SA1110?
CDP	Co-processor data operation	-
CMF	Compare floating point value	Floating Point
CMN	Compare negated values	-
CMP	Compare values	-
CNF	Compare negated floating point values	Floating Point
COS	Cosine	Floating Point
DCx	Define byte (B), halfword (W), word (D), string (S), or floating point (F) value	This is an assembler pseudo-instruction
DVF	Divide	Floating Point
EOR	Exclusive-OR two values	-
EQUx	Define byte (B), halfword (W), word (D), string (S), or floating point (F) value	This is an assembler pseudo-instruction
EXP	Exponent	Floating Point
FDV	Fast Divide	Floating Point
FIX	Convert floating value to an integer	Floating Point
FLT	Convert integer to a floating value	Floating Point
FML	Fast multiply	Floating Point
FRD	Fast reverse divide	Floating Point
LDC	Load from memory to co-processor	-
LDF	Load floating point value	Floating Point
LDM	Load multiple registers	-
LDR	Load register	-
LDRB	Load byte into register	-
LDRH	Load halfword into register	StrongARM
LDRSB	Load signed byte into register	StrongARM
LDRSH	Load signed halfword into register	StrongARM
LFM	Load multiple floating point values	Floating Point
LGN	Logarithm to base e	Floating Point
LOG	Logarithm to base 10	Floating Point
LSL	Logical Shift Left	This is an option, not an instruction
LSR	Logical Shift Right	This is an option, not an instruction
MCR	Co-processor register transfer	-
MLA	Multiply with Accumulate	-
MNF	Move negated	Floating Point
MOV	Move value/register into a register	-
MRC	Co-processor register transfer	-
MRS	Move status flags to a register	ARM 6
MSR	Move contents of a register to the status flags	ARM 6
MUF	Multiply	Floating Point
MUL	Multiply	-
MVF	Move value/float register into a float register	Floating Point
MVN	Move negated	-
NRM	Normalise	Floating Point
OPT	Select assembly options	This is an assembler pseudo-instruction
ORR	Logical OR	-
POL	Polar Angle	Floating Point
POW	Power	Floating Point
RDF	Reverse Divide	Floating Point
RFC	Read FP control register	Floating Point
RFS	Read FP status register	Floating Point
RMF	Remainder	Floating Point
RND	Round to integral value	Floating Point
ROR	Rotate Right	This is an option, not an instruction
RPW	Reverse Power	Floating Point
RRX	Rotate Right with extend	This is an option, not an instruction
RSB	Reverse Subtract	-
RSC	Reverse Subtract with Carry	-
RSF	Reverse Subtract	Floating Point
SBC	Subtract with Carry	-
SFM	Store Muliple Floating point values	Floating Point
SIN	Sine	Floating Point
SMLAL	Signed Long (64 bit) Multiply with Accumulate	StrongARM
SMULL	Signed Long (64 bit) Multiply	StrongARM
SQT	Square Root	Floating Point
STC	Co-processor data transfer	-
STF	Store floating point value	Floating Point
STM	Store multiple registers	-
STR	Store a register	-
STRB	Store a byte (from a register)	-
STRH	Store a halfword (from a register)	StrongARM
STRSB	Store a signed byte (from a register)	StrongARM
STRSH	Store a signed half-word (from a register)	StrongARM
SUB	Subtract	-
SUF	Subtract	Floating Point
SWI	Cause a SoftWare Interrupt	-
SWP	Swap register with memory	ARM 3
TAN	Tangent	Floating Point
TEQ	Test Equivalence (notional EOR)	-
TST	Test and mask (notional AND)	-
UMLAL	Unsigned Long (64 bit) Multiply with Accumulate	StrongARM
UMULL	Unsigned Long (64 bit) Multiply	StrongARM
URD	Unnormalised round	Floating Point
WFC	Write FP control register	Floating Point
WFS	Write FP status register	Floating Point

Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Emulator. RFC and WFC are only provided by hardware floating point systems.
Everything else are bits and pieces that were worth including, shift options and common assembler mnemonics...
Co-processor instructions are listed. However the ARM processors used in RISC OS machines do not support co-processors, and only the virtual co-processor functions present within the chip can be accessed. These provide facilities for setting up the ARM, cache, MMU, etc...